1. Field of the Invention
The present invention relates to a vertical type semiconductor device, such as a vertical type power MOSFET, particularly one which has decreased on-resistance.
2. Description of the Related Art
The conventional vertical type power MOSFETs have in many cases been constructed as shown in FIG. 3 (e.g., see Japanese Unexamined Patent Publication (Kokai) No. 63-254769). When the channel conduction type is of the n type in this structure, a p-type well 13 is formed on the surface of a semiconductor substrate 11 in which the elements will be formed, and n-type source regions 14 of a high concentration are formed in the well 13. An n.sup.+ -type drain region 12 of high concentration is formed at a maintained predetermined depth depending upon the breakdown voltage of the elements. The portion 11 sandwiched between the well 13 and the n.sup.+ -type drain region 12 is called an n-type drift region and has a relatively low concentration.
The breakdown voltage between the drain and source of this element is determined by the thickness of the drift region 11 and thus the impurity concentration, and a thickness and a concentration are selected to satisfy the desired breakdown voltage. When a voltage is applied to a gate 17 disposed over the well 13, an n-type inverted layer is formed on the surface of the semiconductor substrate in the well 13, and an electric current flows between the source and the drain.
In a practical vertical type MOSFET, a portion (cell) denoted by A in FIG. 3 is repetitively arranged to constitute the vertical type MOSFETs. The size a of the portion A is selected to be as small as possible allowed under the manufacturing process or under the element characteristics. This makes it possible to maximize the number of current paths included per unit area.
One of the important characteristics of the vertical power MOSFET is a product (referred to as R.sub.ONS) of element area and on-resistance. If compared on the basis of a predetermined element area, the voltage drop across the source and drain when a current is permitted to flow decreases with a decrease in the value of product, and a reduced amount of electric power is the consumed by the element. The product R.sub.ONS can be decreased by either decreasing the resistance of the element itself or decreasing the element area.
Hatched portions in FIG. 4 represent current paths in the drift region. If viewed in the direction of depth from the surface of the substrate, it will be recognized that a region sandwiched by the wells 13 forms a bottleneck that broadens toward the drain 12. The bottleneck is formed by the effect of a junction-type field-effect transistor (referred to as a JFET) parasitically formed in the semiconductor substrate in the vertical direction. That is, a potential difference develops along the current path due to a resistance component in the drift region, the junction between the well and the drift region is inversely biased by a potential difference between the drift region 11 and the source 14 and well 13 secured to a ground potential, and a depletion layer expands toward the drift region having a relatively low impurity concentration to narrow the current path.
The effect of the JFET is conspicuous with an increase in the voltage applied to the drain or with an increase in the drain current. The resistance of a region upon which the effect of the JFET will act is denoted by R.sub.JFET. The on-resistance R.sub.CELL between the source terminal S and the drain terminal D of a vertical type MOSFET cell can be represented by a resistance R.sub.S of the source region, a channel resistance R.sub.CH, a resistance R.sub.DRI of the drift region, and a resistance R.sub.DRA of the drain region, in addition to the resistance of the region upon which the effect of the JFET will act R.sub.JFET, i.e., EQU R.sub.CELL =R.sub.S +R.sub.CH +R.sub.JFET +R.sub.DRI +R.sub.DRA( 1).
Furthermore, a relation between R.sub.CELL and R.sub.ONS can obviously be given as follows: EQU R.sub.ONS =R.sub.CELL /N (2)
where N denotes a number of cells per unit area.
Referring to FIG. 4, a distance s between the neighboring gates provides a space for making contact with the wiring and for a p.sup.+ -type region 15 that provides potential to the source 14 and well 13. The distance s varies depending upon the precision of processing the formed elements, can be determined if the manufacturing apparatus and, process are specified, and cannot be smaller than a predetermined value.
FIG. 5 shows a relationship between the well distance l and the product R.sub.ONS of element area and on-resistance. As the distance l decreases, the bottleneck of the current path shown in FIG. 3 becomes narrow and R.sub.JFET increases, whereby R.sub.CELL increases more than N, and R.sub.ONS increases. If the distance l is increased, on the other hand, the effect of JFET is weakened but the area increases unnecessarily and R.sub.ONS also increases. As a result, therefore, if the breakdown voltage and the precision of the machining process are determined, there is an optimum distance l at which point the product R.sub.ONS is the smallest as shown in FIG. 5.
In order to further decrease the minimum value of R.sub.ONS shown in FIG. 5, Japanese Unexamined Patent Publication (Kokai) No. 63-254769 proposes a structure that is shown in FIG. 6. According to this structure, a groove 20 is formed in a region sandwiched by the wells 13, and a layer 21 of a high impurity concentration is formed around the groove in order to decrease the resistance of this portion. Therefore, even if the depletion layer expands from the boundary of the well and drift region toward the drift region, the high-impurity-concentration layer 21 around the groove is not depleted. Accordingly, a low resistance is maintained and a low value for R.sub.JFET is maintained. EQU R.sub.CELL =R.sub.S +R.sub.CH +R.sub.DRI +R.sub.DRA ( 3).
As described above, the structure of FIG. 6 makes it possible to suppress an increase in the on-resistance due to the JFET effect. This eventually makes it possible to shorten the distance l between the wells; i.e., R.sub.CELL is decreased without changing the number N of cells and R.sub.ONS is also decreased, as compared with that of the structure of FIG. 3.
The prior art shown in FIG. 6 can be expected to decrease R.sub.ONS more than the prior art shown in FIG. 3. Owing to the progress in machining technology in recent years, however, the distance l between the wells shown in FIG. 4 has now been shortened to several microns for the vertical type low-voltage-breakdown MOSFETs, which have a breakdown voltage of several tens of volts, and the size a of the portion A of FIG. 3 has been reduced to smaller than 20 .mu.m (e.g., Nikkei Electronics, Nikkei BP Co., Jun. 4, 1990, p. 142). Even if the groove 20 is simply formed in the region sandwiched by the wells 13 as shown in FIG. 6, the distance l between the wells must be increased to provide a gap so that the wells 13 will not come in contact with the groove 20. Therefore, the area increases undesirably, and N decreases more than R.sub.CELL decreases as is obvious from the relation (2), and R.sub.ONS increases.
According to the conventional technology shown in FIG. 6, which is effective for decreasing the resistance R.sub.JFET of the bottleneck portion only, the value R.sub.ONS decreases little since the resistance R.sub.DRI of the drift region and the similar resistance of like regions are not decreased. That is, even if high grade machining technology is adapted to the structures of the prior art of FIGS. 3 and 6, it is not possible to decrease the product R.sub.ONS without impairing the breakdown voltage of the element.
Moreover, when the element of the structure shown in FIG. 6 is in a turned-off condition, a high voltage applied to the drain electrode is induced in the channel portion via the drift region 11 and there is an impurity layer 21 of high concentration around the groove, giving rise to the occurrence of breakdown that makes it difficult to obtain a necessary breakdown voltage and, further, causes the gate oxide film 16 to be destroyed.